1. Field of the Invention
The present invention relates to integrated circuit devices. More specifically, the present invention relates to a method and an apparatus for defining signal timing characteristics for an integrated circuit device.
2. Related Art
Modern computing systems operate at ever-higher clock rates and present many challenges to circuit designers. At a clock rate of 1.6 gigahertz, for instance, the clock cycle time is 625 picoseconds. Since signals travel along the traces on a printed circuit board at approximately 180 picoseconds per inch, an extra half an inch of trace length consumes about 14.4 percent of the total cycle time at 1.6 gigahertz. The timing delay associated with extra signal trace length can severely impact the timing margins in a circuit at these high clock rates.
An integrated circuit device has many input/output connections and the signals at these connections are usually related in time. Typically, a designer of an integrated circuit specifies signal timing at external connections to the device. Bonding pads on the semiconductor die that is located within the integrated circuit package are different distances from these external connections. When signals traverse different length paths within the package, the signals arrive at the external connections skewed in time. In order to eliminate timing skew on related signals such as data lines, the signals are often deskewed within the package.
One method of deskewing the signals so they arrive at the external connections at the same time is to add extra trace length within the package through a process called tromboning. While effective at deskewing the signals, tromboning adversely affects density of routing on the package and increases the time required for designing the package and also increases package design complexity.
After the signals have exited the integrated circuit device""s package, they are routed on the printed circuit board to other integrated circuits. It is common for these packages to have hundreds or even thousands of external connections. The printed circuit board designer has an equally perplexing problem routing the signals away from the integrated circuit package to other devices on the printed circuit board. The route that the printed circuit trace takes away from the external connection of the device is termed the xe2x80x9cescape pattern.xe2x80x9d
In order to maintain the timing relationship among the related signals, the printed circuit board designer also resorts to deskewing methods such as tromboning. Deskewing on the printed circuit board also adversely affects the density of routing and design effort in the same way as deskewing within the device package.
For example, FIG. 1 illustrates integrated circuit device 102 coupled to integrated circuit device 104. Only two printed circuit traces, traces 120 and 122, are shown to prevent the diagram from being too cluttered. A practitioner of ordinary skill in the art will readily appreciate that there can be hundreds of printed circuit traces between integrated circuit device 102 and integrated circuit device 104. It is also typical for the printed circuit board to have several layers through which to route the various traces as well.
Die 106 within integrated circuit device 102 is coupled to the external connections, such as external connections 108 and 112, of the integrated circuit device package. The coupling within the package is typically multi-layer like the printed circuit board. Note that die 106 has bonding pads (not shown) for coupling the signals off of the die. In FIG. 1, external connection 108 is coupled to the die by trace 110 while external connection 112 is coupled to the die by trace 118.
External connection 112 is a greater distance from die 106 than is external connection 108. The package designer can compensate for the different distance by tromboning trace 110. This greatly reduces or eliminates the skew between the signals at external connections 108 and 112 such that the signals arrive at external connections 108 and 112 at the same time.
After exiting the integrated circuit device, the signals from external connections 108 and 112 are coupled to printed circuit traces 120 and 122, respectively. Printed circuit traces 120 and 122 route these signals to integrated circuit device 104. The couplings from plane 116 into integrated circuit device 104 are similar to the couplings to integrated circuit device 102 and are not described further.
The printed circuit board designer creates the escape pattern for the signals from external connections 208 and 212. Since it is likely that the path lengths for the various printed circuit traces are different, the printed circuit board designer can also compensate for the different lengths by tromboning as shown at trace 114. Note, however, that both couplings from die 106 to plane 116 have a section of tromboning. The signal passing through external connection 108 is coupled through traces 110 and 120, while the signal passing through external connection 112 passes through traces 118, 114, and 122.
While these couplings bring both signals to plane 116 without skew, both signals are delayed by the use of tromboning, which reduces the available timing margins.
What is needed is a method and apparatus for coupling signals away from an integrated circuit device, which minimizes the use of tromboning on both the package and the circuit board.
One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane. Note that the methods embodied within this system can be performed manually by system designers or can be performed in part or in whole by a computing device programmed to perform the methods.
In one embodiment of the present invention, a second signal line is routed from the semiconductor die within the integrated circuit package to a second external connection of the integrated circuit package. A second signal on the second signal line has a timing relationship with a first signal on the first signal line. Next, the system generates a second escape pattern for a second circuit trace on the printed circuit board from the second external connection to the virtual timing reference plane. Finally, the system establishes a second set of signal timings for a combination of the second signal line and the second circuit trace at the virtual timing reference plane.
In one embodiment of the present invention, the second set of signal timings is substantially equal to the first set of signal timings.
In one embodiment of the present invention the combination of the first signal line and the first circuit trace is designed to minimize manual deskewing.
In one embodiment of the present invention, the combination of the second signal line and the second circuit trace is designed to minimize manual deskewing.
In one embodiment of the present invention, manual deskewing includes tromboning. Tromboning refers to the process of increasing a trace length by causing the trace to move back and forth across its intended path.
In one embodiment of the present invention, a first delay associated with the combination of the first signal line and the first circuit trace is substantially equal to a second delay associated with the combination of the second signal line and the second circuit trace.
In one embodiment of the present invention, the first delay and the second delay are minimized.
In one embodiment of the present invention, the virtual timing reference plane is a plane established outside of a boundary of the integrated circuit device through which connections to the integrated circuit device pass.